Computer buses are generally employed to transfer data between a plurality of elements in a computer system, such as between a microprocessor and RAM, or from a floppy disk drive to a cache. Efficiently designed bus architecture is of increasing concern as the processing speeds of the elements coupled by the buses, such as a processor and a coprocessor, continue to increase. A limiting factor of computer system operation can be the effective rate of data transfer across buses. In some systems, the processing elements processes data faster than the data can be transferred to the processing element.
One form of bus architecture comprises a ring topology. Generally, in a ring topology, information, which can comprise both commands to the processing elements and data employed by the processing elements, is passed from PE to PE in a circular manner.
However, there are disadvantages associated with conventional ring topology. For instance, in conventional systems, a processing element (PE) employed in a data transfer can be unavailable to participate in the transfer of other data between the PE and the ring bus. This unavailability can be from the time a command to perform the data transfer is received by the PE until the time the associated data is transferred between the PE and the ring bus. This unavailability can comprise a number of computer clock cycles.
Furthermore, in a bus system that employs attached processor units (APUs) in a bus ring topology, bandwidth is important. In other words, the ability to have a large amount of data passed at any one time in parallel from APU to APU is a design consideration. In other microprocessing systems that do not employ a ring topology with APUs, latency is more of a concern.
Therefore, a need exists for a bus ring architecture that overcomes at least some of the deficiencies of conventional systems.